Nonvolatile memories, represented by flash memory, are widely used in various products, such as storage or communication devices such as mobile phone, laptop, palmtop and solid-state hard disk, and the like, due to their advantages such as data-holding capability even though power supply is cut off, as well as the capability of erasing and writing data for multiple times, etc. Presently, flash memories have occupied most of the market share of nonvolatile semiconductor memories, wherein NOR flash memories are widely used in code storage chips of mobile terminals such as mobile phones and the like, due to their high speed for random access. However, the conventional NOR flash memory adopts channel hot electron injection method, which has two significant limitations: firstly, the efficiency of the channel hot electron programming is very low and thus the power consumption is very high; secondly, a relatively high bit line voltage (usually, 4-5V) is needed in such a programming method, therefore, in order to prevent a punch-through phenomenon from occurring under such a high bit line voltage, the channel length of the memory cell in the conventional NOR flash memory array cannot be reduced rapidly, thus the decrease of the memory cells in size and the increase of the storage density of the NOR flash memory are limited. Due to the two limitations, it is difficult for the NOR flash memories to meet the requirements for large capacity, low cost, low power consumption nonvolatile memory technology.
For the disadvantage that the power consumption is high in the channel hot electron programming of the NOR flash memories, a split-gate programming method is used to reduce power consumption in references [1], [2] and [3]. In such a technology, different voltages are applied to the gates, that is, a relatively low voltage is applied to the gate close to the source terminal and a high voltage is applied to the gate close to the drain terminal, thus the efficiency for programming can be improved so as to reduce the power consumption. However, all of the existing split-gate technologies are designed with respect to one cell, making the process to be complex. Particularly, a relatively large difference of the programming voltages between the source terminal and the drain terminal is necessary in such a memory cell, thus limiting the shortening of the channel of the flash memory cell.
For the challenge that the shortening of the cell channel is limited due to the high bit line voltage required for the channel hot electron programming of the NOR flash memories, a method that two adjacent cells on the same word line are both involved in the programming is used in the references [4] and [5], in which such a bit line voltage for programming is shared by two adjacent cells and therefore a source/drain punch-through problem in a single device can be effectively avoided. However, such a technology is based on the conventional NOR-type array (as shown in FIG. 1) or NROM array, in which word lines and bit lines are perpendicular to each other and thus the two adjacent cells both involved in the programming share one word line that controls the voltages of control gates, making it impossible for the split-gate programming method to be used in these arrays and thereby there exists a problem that the power consumption for programming is limited.
In a word, that how to improve the capability of reducing the size of the flash memory and decrease the power consumption is an urgent problem to be solved in the flash memory technology.